1. Field of the Invention
The present invention relates to a multilayered power supply line of an MTM (Metal-Insulator-Metal) structure, which supplies power to an I/O (Input/Output) buffer and an internal circuit in a semiconductor integrated circuit, and a method of laying out the multilayered power supply line.
This application is counterpart of Japanese patent application, Serial Number 397724/2003, filed Nov. 27, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
As general multilayered power supply lines each suitable for use in a semiconductor integrated circuit, which supply power to I/O buffers and internal circuits, there have heretofore been known one laid out with a wiring metal of one layer being provided in such a power supply line as shown in FIG. 9, and one laid out using a multilayered wiring metal such that the impedance of a power supply line becomes low. A sectional view of the power supply line shown in FIG. 9, which is taken along a dotted line 98, is shown in FIG. 10.
As such a multilayered wiring metal, there has been known a power supply line described in the following Patent Document 1, for example. In the present power supply line, a first metal layer is added to an area free of an I/O buffer of a chip corner unit, and parallel plate condensers are respectively formed between the first metal layer, and a VDD power supply line and a GND power supply line to increase capacity, thereby making it possible to reduce noise caused by switching of the I/O buffer.
Since a first power supply wiring layer supplied with a power supply or source potential from an external power supply, and a second power supply wiring layer supplied with a ground potential are formed in multilayer form in a semiconductor device described in the following Patent Document 2, the wiring resistances of the first and second power supply wiring layers can be reduced. Therefore, a power supply or source potential low in impedance and a ground potential can be supplied to each circuit block in an internal circuit.
Patent Document 1
Japanese Laid-Open patent No. 1997-246476.
Patent Document 2
Japanese Laid-Open patent No. 2000-311964
Methods such as expanding of a wiring width, multilayering of wirings as in the case of the above-described Patent Documents 1 and 2 or the like have been used in the multilayered power supply lines employed in the semiconductor integrated circuits in order to reduce impedance.
However, a chip area increases with the expansion of the wiring width, and wiring's multilayering encounters difficulties in wiring other signal lines. Since the VDD and GND power supply lines are relatively small in capacity, switching noise is apt to occur in the semiconductor integrated circuit.